About
module counter4(clk,reset,out);
input clk,reset; output[3:0] out; reg[3:0] out;
always @(posedge clk) begin
if(reset) begin
out <= 0;
end
else begin
out <= out + 1;
end
end
endmodule
module d_flipflop(d,clk,q,q_bar);
input d,clk;
output q,q_bar;
reg q,q_bar;
always @(posedge clk) begin
q = d;
q_bar = ~q;
end
endmodule
module mux4_tb;
reg A,B,I0,I1,I2,I3;
wire out;
integer i;
mux4 m1(I0,I1,I2,I3,A,B,out);
initial begin
$monitor("I0 = %b, I1 = %b, I2 = %b, I3 = %b, A = %b, B = %b,out = %b",I0,I1,I2,I3,A,B,out);
for(i=0;i<64;i = i+1) begin
1
{I0,I1,I2,I3,A,B} = i;
end
1
$finish;
end
endmodule
module mux4(I0,I1,I2,I3,A,B,out);
input I0,I1,I2,I3,A,B;
output reg out;
always @(I0 or I1 or I2 or I3 or A or B) begin
if(A == 0 && B == 0) begin
out = I0;
end
else if (A == 0 && B == 1) begin
out = I1;
end
else if(A == 1 && B == 0) begin
out = I2;
end
else begin
out = I3;
end
end
endmodule
module counter4_tb;
reg clk,reset;
wire[3:0] out;
counter4 c1(clk,reset,out);
initial begin
$monitor("clk = %b, reset = %b, out = %b",clk,reset,out);
clk = 1;
reset = 1;
1
reset = 0;
31
reset = 1;
$finish;
end
always #1 clk = ~clk;
endmodule
module jk_flipflop_tb;
reg j,k,clk;
wire q,q_bar;
integer i;
jk_flipflop j1(j,k,clk,q,q_bar);
initial begin
$monitor("j = %b,k = %b,clk = %b,q = %b, q_bar = %b",j,k,clk,q,q_bar);
for(i=0;i<8;i=i+1) begin
1
{j,k,clk} = i;
end
1
$finish;
end
endmodule
module jk_flipflop(j,k,clk,q,q_bar);
input j,k,clk;
output q,q_bar;
reg q,q_bar;
initial begin
q = 0;
q_bar = 0;
end
always @(posedge clk) begin
if(j == 0 && k == 0) begin
q = q;
q_bar = q_bar;
end
else if(j == 0 && k == 1) begin
q = 0;
q_bar = ~q;
end
else if(j == 1 && k == 0) begin
q = 1;
q_bar = ~q;
en…
module d_flipflop_tb;
reg d,clk;
wire q,q_bar;
integer i;
d_flipflop d1(d,clk,q,q_bar);
initial begin
$monitor("d = %b,clk = %b,q = %b, q_bar = %b",d,clk,q,q_bar);
for(i=0;i<4;i=i+1) begin
1
{d,clk} = i;
end
1
$finish;
end
endmodule