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module decoder( enable, in, op );
input[1:0] in; input enb; output[3:0] op;
wire [1:0] in; wire enb; reg [3:0] op;
wire inn0, inn1; not(inn0, in[0]); not(inn1, in[1]); and(op[0], inn0, inn1); and(op[1], in[0], inn1); and(op[2], inn0, in[1]); and(op[3], in[0], in[1]);
end end endmodule
module decoder( enb, in, op );
input[1:0] in; input enb; output[3:0] op;
wire [1:0] in; wire enb; reg [3:0] op;
always @(in or enb) begin op=0; op[in]=1;
end endmodule
module decoder_tb;
reg [1:0] in; reg enb; wire [3:0] op;
integer i;
decoder my_dc( enb, in, op );
initial begin
1 $monitor("enable = ", enb, " | Input = %b", in, " | output = %b ", op );
assign enb = 1; for( i = 0; i <= 3; i = i + 1) begin in = i;#1 $display("-----------------------------------------"); end
end endmodule
module demux( select, in, op );
input[1:0] select; input in; output[3:0] op;
wire in; wire[1:0] select; reg[3:0] op;
always @(in or select) begin op=0; op[select]=in;
end endmodule
module demux1( select, in, op );
input[1:0] select; input in; output[3:0] op;
wire in; wire[1:0] select; reg[3:0] op;
integer i; initial begin for(i=0;i<=3;i=i+1) begin if(select==i) begin op[i] = in; end else begin op[i] = 0; end
end end
endmodule
module demux_tb;
reg in; reg [1:0] select; wire [3:0] op;
integer i;
demux1 my_mux( select, in, op );
initial begin
1 $monitor("Input = %b", in, " | select = %b", select, " | op = ", op );
for( i = 0; i <= 4; i = i + 1) begin select = i; in = 0; #1; in = 1; #1; $display("-----------------------------------------"); end
end
endmodule
module enc1( select,y);
input[7:0] select; output[2:0] y;
wire[7:0] select; reg [2:0] y;
integer i; always @(select) begin y=select; for (i=0; i<=7;i=i+1) begin if(select[i]==1) begin y=i; end end end
endmodule
module enc;
reg[7:0] select; wire[2:0] y;
integer i;
enc1 my( select,y);
initial begin
$display("Input = 0 | select = X | y = 000"); $display("-----------------------------------------");
1 $monitor(" | select = %b", select, " | y = %b", y );
for( i = 0; i <= 7; i = i + 1) begin
select=0;
select[i] = 1;
#1;
$display("-----------------------------------------");
end
$finish;end
endmodule
// Verilog testbench for 4 to 1 Multiplexer // by Harsha Perla for http://electrosofts.com // Comments to: harsha@electrosofts.com // Available at http://electrosofts.com/verilog
module mux_tb;
reg[3:0] d; reg[1:0] select; wire q;
integer i;
mux6 my_mux( select, d, q );
initial begin
1 $monitor("d = %b", d, " | select = ", select, " | q = ", q );
for( i = 0; i <= 15; i = i + 1) begin d = i; select = 0; #1; select = 1; #1; select = 2; #1; select = 3; #1; $display("-----------------------------------------"); end $finish; end endmodule
module mux_tb;
reg[3:0] d; reg[1:0] select; wire q;
integer i;
mux1 my_mux( select, d, q );
initial begin
1 $monitor("d = %b", d, " | select = %b", select, " | q = ", q );
for( i = 0; i <= 15; i = i + 1) begin d = i; select = 0; #1; select = 1; #1; select = 2; #1; select = 3; #1; $display("-----------------------------------------"); end
end endmodule
module mux1( select, d, q );
input[1:0] select; input[3:0] d; output q;
wire q; wire[1:0] select; wire[3:0] d;
assign q = d[select];
endmodule
module mux1( select, d, q );
input[1:0] select; input[3:0] d; output q;
wire q; wire[1:0] select; wire[3:0] d;
assign q = d[select];
endmodule
module mux2( select, d, q );
input[1:0] select; input[3:0] d; output q;
reg q; wire[1:0] select; wire[3:0] d;
always @(d or select) q = d[select];
endmodule
module mux1( select, d, q ); input[1:0] select; input[3:0] d; output q;
wire q; wire[1:0] select; wire[3:0] d; wire sn1,sn0,w1,w2,w3,w4;
not(sn0,select[0]); not(sn1,select[1]); and(w1,d[0],select[0],select[1]); and(w2,d[1],sn0,select[1]); and(w3,d[2],select[0],sn1); and(w4,d[3],sn0,sn1); or(q,w1,w2,w3,w4);
endmodule
// Verilog code for Multiplexer implementation. // by Harsha Perla for http://electrosofts.com // harsha@electrosofts.com // Available at http://electrosofts.com/verilog
module mux3( select, d, q );
input[1:0] select; input[3:0] d; output q;
reg q; wire[1:0] select; wire[3:0] d;
always @( select or d ) begin if( select == 0) q = d[0];
if( select == 1) q = d[1];
if( select == 2) q = d[2];
if( select == 3) q = d[3]; end
endmodule
module mux4( select, d, q );
input[1:0] select; input[3:0] d; output q;
reg q; wire[1:0] select; wire[3:0] d;
always @( select or d ) begin case( select ) 0 : q = d[0]; 1 : q = d[1]; 2 : q = d[2]; 3 : q = d[3]; endcase end
endmodule
module mux5( select, d, q );
input[1:0] select; input[3:0] d; output q;
wire q; wire[1:0] select; wire[3:0] d;
assign q = ( select == 0 )? d[0] : ( select == 1 )? d[1] : ( select == 2 )? d[2] : d[3];
module mux6( select, d, q );
input[1:0] select; input[3:0] d; output q;
reg q; wire[1:0] select; wire[3:0] d;
always @( select or d) begin q = ( \(select[0] & \)select[1] & d[0] ) | ( select[0] & \(select[1] & d[1] ) | ( \)select[0] & select[1] & d[2] ) | ( select[0] & select[1] & d[3] ); end
endmodule
module mux7( select, d, q );
input[1:0] select; input[3:0] d; output q;
wire q, q1, q2, q3, q4, NOTselect0, NOTselect1; wire[1:0] select; wire[3:0] d;
not n1( NOTselect0, select[0] ); not n2( NOTselect1, select[1] );
and a1( q1, NOTselect0, NOTselect1, d[0] ); and a2( q2, select[0], NOTselect1, d[1] ); and a3( q3, NOTselect0, select[1], d[2] ); and a4( q4, select[0], select[1], d[3] );
or o1( q, q1, q2, q3, q4 );
endmodule